1. Field of the Invention
This invention relates to implementations of an analog-to-digital (A/D) converter that employ cascaded phase-reversing switches for converting the amplitude of an analog signal to a preselected N-Bit binary code and, more particularly, to such implementations that may use microwave-phase-logic (MPL) integrated-circuits suitable for operating on an analog signal having a multi-Gigahertz (GHz) bandwidth.
2. Description of the Prior Art
Incorporated by reference herein is U.S. Pat. No. 5,528,175, entitled “Devices for Implementing Microwave Phase Logic,” which issued Jun. 18, 1996 and is assigned to the same assignee as the present invention. U.S. Pat. No. 5,528,175 discloses the MPL implementation of both a full-adder device and a memory element that can operate as a phase latch.
Further, incorporated by reference herein is U.S. Pat. No. 6,008,748, entitled “Microwave Phase Logic Implementation of an Analog-to-Digital Converter,” which issued Dec. 28, 1999 and is assigned to the same assignee as the present invention. The implementation disclosed in U.S. Pat. No. 6,008,748 is directed to serial pipelined A/D converters that propagate both the analog signal and a reference, with the amplitude of the reference asymptotically approaching the amplitude of the analog signal but with a reversal of polarity or phase.
Known are flash A/D converters that employ an array of amplitude comparators for comparing, in ascending order, the amplitude of each of a plurality of reference-value inputs with the amplitude value of an analog signal input. If the amplitude of the signal input to any one of the comparators exceeds the amplitude of the reference-value input to that one comparator, the output from that comparator will be a binary “1” value. If the amplitude of the signal input to any one of the comparators does not exceed the amplitude of the reference-value input to that one comparator, the output from that comparator will be a binary “0” value. The output from the entire array of amplitude comparators is known as a “thermometer code.” A flash A/D converter then needs a thermometer code to binary code converter (one of several known ways of implementing this comprises a complex array of many FULL ADDER logic devices) to decode the thermometer code and convert it to a selected N-Bit binary code output from the flash A/D converter.
Flash A/D converters also may be implemented employing an array of MPL phase-reversing switches as comparators, instead of employing amplitude comparators. In this case, the MPL FULL ADDER logic device disclosed in the aforesaid is U.S. Pat. No. 5,528,175 may be employed in the implementation of the complex array of many FULL ADDER logic devices to convert the thermometer code to a selected N-Bit binary code output from the flash A/D converter.
Known is a doubly-balanced mixer comprising a four-diode ring. Also known since 1967 is a doubly-balanced mixer called a Gilbert cell mixer that employs four transistors instead of four diodes. As known, a Gilbert cell mixer may form the basis of a common integrated-circuit bipolar building block. Because a Gilbert cell mixer exhibits gain (and a four-diode ring doubly-balanced mixer does not), a Gilbert cell mixer is the preferred implementation of each phase-reversing switch of a flash A/D converter and the cascaded phase-reversing switches employed in the MPL A/D converter implementation of the present invention. However, because conventional double-balanced mixers do not switch phase when two baseband inputs thereto are substantially equal, A/D converter implementation of the present invention with conventional double-balanced mixers needs phase latches.